Browse Prior Art Database

Compression Cache Miss Bypass in a Memory Subsystem

IP.com Disclosure Number: IPCOM000117467D
Original Publication Date: 1996-Mar-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 55K

Publishing Venue

IBM

Related People

Blackmon, HL: AUTHOR [+2]

Abstract

A method for improving the performance of Main Store Memory Subsystems that use Data Compression is disclosed. The Dynamic Random Access Memory (DRAM) operations required to decompress data are interleaved with DRAM operations that involve data which does not need to be decompressed.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 65% of the total text.

Compression Cache Miss Bypass in a Memory Subsystem

      A method for improving the performance of Main Store Memory
Subsystems that use Data Compression is disclosed.  The Dynamic
Random Access Memory (DRAM) operations required to decompress data
are interleaved with DRAM operations that involve data which does not
need to be decompressed.

      A concept in the area of Main Store Memory Subsystems is Data
Compression.  Compression is used to reduce the amount of physical
memory needed for system requirements.

      This invention assumes that the Memory Subsystem can buffer
more than one Read command at a time.

      This invention assumes that the interface between the
Processors and the Memory Subsystem will allow the data for Read
commands to be returned to the Processors out of the order that the
commands were sent.

      This invention assumes that the Compression scheme divides the
physical memory into two regions:  (Hit) a cache of de-compressed
data, and (Miss) data that is compressed.

      This invention assumes that the function of decompressing data
is made up of several DRAM Read/Write accesses.  It also assumes that
there is a substantial amount of data manipulation that must occur
before the data is fully decompressed and can be sent to the
Processor.

      The invention is to provide a command queueing mechanism in the
Memory Subsystem that allows commands that access a Hit region to by
pass and be executed ahead of p...