Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Concept for Minimized Data-in-Access in Random Access Memory with Write-Through Function

IP.com Disclosure Number: IPCOM000117480D
Original Publication Date: 1996-Mar-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 4 page(s) / 110K

Publishing Venue

IBM

Related People

Buettner, S: AUTHOR [+4]

Abstract

There are two basic concepts used to receive the data-in signals, and set the bitlines accordingly: 1. Static data-in circuit scheme: The data-in signals are received, distributed and powered by balanced circuits. Balanced with respect to "ON" and "OFF" delay. The achievable data-in setup time can be calculated as: -(T(SSA) - TD(SSA) - TD(DI) - Margin(DI/SSA)) SSA = set sense amplifier T(SSA) = time array clock to SSA TD(SSA) = variation of SSA TD(DI) = delay of data-in circuits (See Timing Chart 1). 2. Precharged data-in circuit scheme: The internal data-in signals are precharged to a restore level at the end of each cycle.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Concept for Minimized Data-in-Access in Random Access Memory with
Write-Through Function

      There are two basic concepts used to receive the data-in
signals, and set the bitlines accordingly:
  1.  Static data-in circuit scheme:  The data-in signals are
received,
       distributed and powered by balanced circuits.  Balanced with
       respect to "ON" and "OFF" delay.  The achievable data-in setup
       time can be calculated as:
      -(T(SSA) - TD(SSA) - TD(DI) - Margin(DI/SSA))
      SSA = set sense amplifier
      T(SSA) = time array clock to SSA
      TD(SSA) = variation of SSA
      TD(DI) = delay of data-in circuits
      (See Timing Chart 1).
  2.  Precharged data-in circuit scheme:  The internal data-in
signals
       are precharged to a restore level at the end of each cycle.
       These signals will then be set according to the data-in input
       signals, with a strobe signal which is derived from the array
       clock.
      The data-in setup time =
      -(T(SSA) - TD(SSA) - TD(DI) - Margin(DI/SSA) - TD(STR) -
       Margin(DI/STR))
      TD(STR) = variation of strobe
      (See Timing Chart 2).

Advantage of case A:
  Simple circuitry, margin DI/SSA controllable by DI timing.

Disadvantage of case A:
  o  relatively large DI circuit delay
  o  large margin required since separate ckt./delay paths for DI and
      SSA (no tracking)
  o  large area for circuits needed

Advantage of case B:
  Fast circuit delay due to precharged circuits.

Disadvantage of case B:
  o  The signal propagation through both the SSA-path and the
      DI-strobe path is started by the array-clock.  Since the
      implementation of both paths is completely independent of each
      other, additional timing margin is required to compensate for
bad
      tracking.
  o  The DI-strobe timing is extremely critical.  If the strobe
      comes too early, wrong data will be latched.  This error is
      not recoverable even under fast process conditions.

      To avoid the additional necessary...