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Low-Cost 80186 Bus Cycle Bridge to High-Performance Microcontroller

IP.com Disclosure Number: IPCOM000117486D
Original Publication Date: 1996-Mar-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 6 page(s) / 140K

Publishing Venue

IBM

Related People

Co, G: AUTHOR [+2]

Abstract

Disclosed is a method of implementing a low cost, quick turn logic bridge, that allows phasing a new faster microcontroller technology into an exhausting design without having to redesign the peripheral logic. The concept is presented by an application example which incorporates an AM186EM-40MHZ as a replacement for a 80C186 20MHZ microcontroller. The unchanged peripheral logic in the design includes two Application Specific Integrated Circuits (ASIC) chips.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 53% of the total text.

Low-Cost 80186 Bus Cycle Bridge to High-Performance Microcontroller

      Disclosed is a method of implementing a low cost, quick turn
logic bridge, that allows phasing a new faster microcontroller
technology into an exhausting design without having to redesign the
peripheral logic.  The concept is presented by an application example
which incorporates an AM186EM-40MHZ as a replacement for a 80C186
20MHZ microcontroller.  The unchanged peripheral logic in the design
includes two Application Specific Integrated Circuits (ASIC) chips.

      The logic bridge creates a "20  MHz 80C186" interface for the
two chips from the outputs of the new 40 Mhz microcontroller.  The
bridge calls for a Programmable Logic Device (PLD), 2 address
buffers, and 2 data transceivers.

      A Chip_Multiplex_Address_Data required for the chips was
generated from the microcontroller Address bus and the
microcontroller data bus.  The address portion of the
Chip_Multiplex_Address_Data bus uses 2 address buffers with their
outputs controlled by the PLD.  Similarly, the data portion of the
Chip_Multiplex_Address_Data bus uses 2 data transceivers with their
outputs controlled by the PLD.  A block diagram of the design
follows.

      Pictured on the block diagram, one can see that some of the key
control signals to the chips are:  Chip_ALE; -Chip_RD; and -Chip_WR.
The control signals between the microcontroller and the PLD that are
not labeled in the block diagram are:  MPALE; -MPRD; -MPWR; ARDY; and
the Chip_Selects.  Once the address and data flow was established,
the next step is to create a state machine in the PLD to make the two
interfaces communicate.  The timing diagrams, Figs. 1 through 4,
detail how the interface behaves for cycles that have valid
Chip_Selects (-PCSx) and cycles that do not access the chips.  The
ready function (ARDY) of the microntroller is used to add additional
wait states for cycles that access the chips.  Note that the cycles
to one of the chips, chip A, requires more wait states than the
cycles to the other chip, chip B.

The basic function of the PLD state machine is as follows:
  1.  Use the MPALE signal to...