Browse Prior Art Database

Differential Pass-Gate Circuits

IP.com Disclosure Number: IPCOM000117499D
Original Publication Date: 1996-Mar-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 6 page(s) / 157K

Publishing Venue

IBM

Related People

Ji, J: AUTHOR [+2]

Abstract

Complex logic function with a great number of input requires a large number of stages of circuits to perform the function. This can be poor in circuit performance and also need a large circuit area as well as power.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Differential Pass-Gate Circuits

      Complex logic function with a great number of input requires a
large number of stages of circuits to perform the function.  This can
be poor in circuit performance and also need a large circuit area as
well as power.

      An object of the present invention is to provide a new
high-performance circuit family for implementing complex logic
functions where many inputs are needed to generate few outputs and
where the true and complement outputs are symmetrical.  Fig. 1 is a
schematic block diagram of an embodiment of a differential pass-gate
circuit illustrating the principles of the present invention.

      The circuit of Fig. 1 is unique compared with prior art
differential schemes.  The major difference is that the logic blocks
3 and 4 are implemented with pass-gates (pass-transistors) and that
the logic block 3 and 4 are not limited to only pull-down trees.  The
logic blocks 3 and 4 are structured such that when block 3 pulls down
node 5 block 4 pulls up node 6 and vice visa, both through
pass-transistors.  Because of the speed advantage, the blocks 3 and 4
are usually formed with n-channel devices.  However, n-channel
devices are not capable of pulling a node all the way up to Vdd;
therefore, a cross-coupled p-device pair 1 and 2 are used to finish
the pull-up process.

      Fig. 1 is a schematic block diagram of an embodiment of a
differential pass-gate circuit illustrating the principles of the
present invention.  Fig. 2 is a schematic block diagram of an
embodiment of a 16-input XOR circuit implemented with the present
invention.  Fig. 3 is a schematic block diagram of an embodiment of a
16-way multiplexer.

      In prior art differential circuits, the logic blocks at
positions of 3 and 4 can only pull nodes 5 or 6 down to ground.  For
example, when one side of the circuit, the side of node 5, is on
(conducting) it pulls the corresponding node 5 down towards ground
and the other side, in this case 6, is off, not doing anything.  The
pull up of the other node, in this example 6, is only performed by
the p-device, in this example 2, after the potential at node 5 is
sufficiently low.  In the present invention, on the other hand, when
block 3 is on pulling node 5 downwards the other block 4 is also on
pulling node 6 upwards.  Therefore, the transition delay is thus
reduced.

      There is yet another problem with prior art differential
circuits where only pull down functions are provided in the logic
blocks.  When node 5 is at ground potential and node 6 is at Vdd and
the next state needs to flip both of these nodes, block 4 is on and
starts to pull down node 6.  However, block 3 is off and hence node 5
remains at ground potential.  Since the ...