Browse Prior Art Database

Programmable Logic Array Worst Case Negative-OR Procedure

IP.com Disclosure Number: IPCOM000117520D
Original Publication Date: 1996-Mar-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 84K

Publishing Venue

IBM

Related People

Cox, DT: AUTHOR [+2]

Abstract

A method is disclosed for determining how many product terms of a static Programmable Logic Array (PLA) on a given OR output line are held down by only one input device. This method checks all possible cases but in much less time than an exhaustive search. This is needed to assure the OR array lines are not incorrectly pulled down due to soft-threshold effects.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Programmable Logic Array Worst Case Negative-OR Procedure

      A method is disclosed for determining how many product terms of
a static Programmable Logic Array (PLA) on a given OR output line are
held down by only one input device.  This method checks all possible
cases but in much less time than an exhaustive search.  This is
needed to assure the OR array lines are not incorrectly pulled down
due to soft-threshold effects.

      Static PLAs contain a circuit design that can cause
soft-threshold problems in the OR array.  Static PLAs use weak PFET
devices to hold product term lines high when the product term's NFETs
are off (the PFETs are always on).  The devices are sized such that
the AND-array NFETs are strong enough to pull the product term
voltage down below the Vt of the OR-array NFETs.  For performance
reasons, the product term down-level should be as high as possible,
but it must not be so high as to turn on the OR-array NFETs.  When
the FETs are sized, the product term voltage is a function of Vdd and
both the product term voltage and the Vt of the OR devices is a
function of process.  This problem is compounded by the possibility
of multiple product terms, all held down by a single AND-array NFET,
all gating OR-array NFETs on the same output line.  At high power
supply voltages, there may be many OR-array NFETs leaking current to
GND pulling an OR-array output line low.  This is a function of the
logic implemented in the PLA and is, therefore, difficult to design
for.

      Testing for wide NOR conditions:  The easiest way to address
this is to assume that any product term on a given OR line could be
held down by a single NFET.  This is pessimistic because the
AND-array logic usually makes this impossible (i.e., there is no
combination of input signals that make it possible).  The next
easiest solution is to test all input patterns and log the worst-case
condition of single-pull-down product terms.  This solution runs in
approximately (2^n * p) time where n is the number of inputs and p is
the number of product terms.  This solution is unacceptable due to
run-time as (n) gets above 20 or so.

      Given the knowledge of how many single-pull-down product terms
the PLA can handle without pulling OR-array lines down (defined by
the device sizing and simulation), the following approach can be
taken:

      Assume set ZERODOWN contains all product terms on a given
OR-array line.  Set the first PLA input bit to a 1.  For all product
terms that have an NFET now turn...