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Structured Hierarchial Approach to Verify a Hardware Design

IP.com Disclosure Number: IPCOM000117522D
Original Publication Date: 1996-Mar-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 76K

Publishing Venue

IBM

Related People

Carter, AM: AUTHOR [+3]

Abstract

Assume a design that consists of two units of logic that communicate across an interface. Unit simulation would be performed on the two units by replacing the logic for a unit with a behavior, first for one unit, then for the other unit. Two behaviors are created. Each behavior must fulfill three roles: a) Stimulate the interface b) Check responses from the other unit c) Check the interface protocol.

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Structured Hierarchial Approach to Verify a Hardware Design

      Assume a design that consists of two units of logic that
communicate across an interface.  Unit simulation would be performed
on the two units by replacing the logic for a unit with a behavior,
first for one unit, then for the other unit.  Two behaviors are
created.  Each behavior must fulfill three roles:
  a) Stimulate the interface
  b) Check responses from the other unit
  c) Check the interface protocol.

      A critical weakness of this structure is that the interface
checking is imbedded in the unit behavior and has to be implemented
in each behavior.  This allows the possibility that the interface
will be modelled differently in each behavior.  This could result in
the two units not being able to operate when directly attached.

      In the past, there has been no unified method of functionally
verifying a complete hardware design, such as a processor chip or
multiple chips, in a system design.  Methods and tools for doing this
were disjoined, made up of discontinuous and discrete pieces.  These
methods and tools could not be carried forward hierarchically in
succession from the verification of the smaller design sub-units up
through the whole system.

      When the new simulation environment is created that contains
both units, the behaviors for the unit environments are not
compatible, and their function cannot be easily reused.
Specifically, the unit simulation environment should be structured to
allow the following functions to be reused:
  a) Check responses from the other unit
  b) Check the interface protocol.

      Create a structured verification methodology, whereby a
simulation environment is created which allows the hardware to be
verified against a set of requirements, the hardware initially being
as small as a sub-unit and then expanded in incremental steps to
include the complete system.  The verification of each incremental
piece can pr...