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Level-Sensitive Scan Design Testing of Self-Resetting Complementary Metal-Oxide Semiconductor Circuits

IP.com Disclosure Number: IPCOM000117526D
Original Publication Date: 1996-Mar-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 4 page(s) / 146K

Publishing Venue

IBM

Related People

Chappell, TL: AUTHOR [+2]

Abstract

This disclosure describes solutions to problems encountered when LSSD test techniques were applied to self-resetting CMOS circuits designed for the Bellatrix/630 processor chip.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 43% of the total text.

Level-Sensitive Scan Design Testing of Self-Resetting Complementary
Metal-Oxide Semiconductor Circuits

      This disclosure describes solutions to problems encountered
when LSSD test techniques were applied to self-resetting CMOS
circuits designed for the Bellatrix/630 processor chip.

      Self-Resetting CMOS circuits designed for the Bellatrix/630
processor chip had some clocking characteristics that made it very
difficult to perform LSSD scan tests on these circuits.  The
following is a summary of these characteristics:
  a) The SRCMOS latches are precharged every cycle so that the latch
      content, after being launched, would be reset due to the
      precharge of the latch in preparation for next cycle
evaluation.
      This resetting of the latch data was a problem during LSSD scan
      testing because the latch, after being scanned with a
particular
      data value, would reset and the scanned data would be lost.
  b) Because of the nature of the SRCMOS circuits, in that a
precharge
      is needed on every cycle and because this precharge timing is
      tied to the global clock that clocks the SR logic, it was
      necessary to require the global clock, CLKG, to be free running
      at all times so that the circuit performs as intended.  This
      requirement of having a free running CLKG caused a
      synchronization problem because the launching clock, CLKL,
which
      is derived from CLKG as shown in Fig. 1, could not overlap with
      the rising edge of the scan clock to the master latch, CLKA.
      CLKA was a lot slower than CLKG and had a somewhat sloppy
wiring.
      The problem was that the the rising edge of CLKA, if allowed to
      overlap with CLKL, could cause some indeterminate latch value
to
      be launched into the SR logic stages and invalidate the test
      measurement taken at the receiving latch.  Synchronization of
the
      rising edge of CLKA with respect to CLKG and routing CLKA
across
      the chip within a window accuracy of 200 ps was practically
      impossible.  The other option of delaying the rising edge of
CLKA
      until after the falling edge of CLKL was also extremely
difficult
      to implement reliably.
  c) The problem of orthogonal latches being scanned with
      non-orthogonal test vectors.  An orthogonal register is a
      register that is restricted to containing only orthogonal data
      vectors.  An orthogonal data vector, in its simplest
definition,
      is a vector of all 0s except for one and only one data element.
      This definition can be extended to include all sorts of
      restrictions as to what the data content of a register can be.
      For example, a register of 8 bits can only acquire the
following
      orthogonal data vectors 000000XX with bits XX being allowed to
      h...