Browse Prior Art Database

Method of Guided Global Wiring

IP.com Disclosure Number: IPCOM000117540D
Original Publication Date: 1996-Mar-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 4 page(s) / 100K

Publishing Venue

IBM

Related People

Miyoshi, A: AUTHOR [+2]

Abstract

Disclosed is a method of Guided Global Wiring which is useful to embed wires, especially global wires, effectively and smoothly in a custom chip. This new method is to guide wiring by putting a dummy block, which is called the GUIDE BLOCK, on expected positions and to make connections with the auto-wire program to pass through this GUIDE BLOCK. As a result, the global wires can be effectively embedded in a chip as expected.

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This is the abbreviated version, containing approximately 53% of the total text.

Method of Guided Global Wiring

      Disclosed is a method of Guided Global Wiring which is useful
to embed wires, especially global wires, effectively and smoothly in
a custom chip.  This new method is to guide wiring by putting a dummy
block, which is called the GUIDE BLOCK, on expected positions and to
make connections with the auto-wire program to pass through this
GUIDE BLOCK.  As a result, the global wires can be effectively
embedded in a chip as expected.

      In the basic methodology of the custom chip design, the macros
which are involved in a chip are designed first, and after generating
all macros, they are properly placed on the designated chip image.
Finally, those macros are connected as required by the auto-wire
program.

The following shows the procedure of the physical design for custom
chip:
  o  Detailed macro design (place and wire)
  o  Place designed macros in a chip
  o  Wire between macros in a chip (Global Wiring)

      The new method of Guided Global Wiring can be applied at the
global wiring phase.  The Guided Global Wiring allows us to perform
smooth and flexible wiring by using of placing GUIDE BLOCKs and the
auto-wire.  The GUIDE BLOCK which is used in this method is defined
and featured as described below:  (Fig. 1).
  o  The GUIDE BLOCK has no device and no logical function.
  o  The GUIDE BLOCK internally contains only wiring images as shown
      in Fig. 1.
  o  The size of the GUIDE BLOCK is flexible and free (1 bit to n
      bit).
  o  The number of the GUIDE BLOCKs to be used in the same design is
      unlimited.
  o  The GUIDE BLOCK is easy to newly define in each specific chip
      design.

In this method with the GUIDE BLOCK, the wiring procedure is shown as
follows:
  o  Placement is completely...