Browse Prior Art Database

Technique for Gaining Indefinite Access to Peripheral Component Interconnect* Bus Resource

IP.com Disclosure Number: IPCOM000117564D
Original Publication Date: 1996-Mar-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Related People

Curry, SE: AUTHOR

Abstract

Disclosed is a technique which enables a PCI bus master to gain indefinite access to the multiplexed address/data lines of the PCI local bus. This is accomplished by initiating a configuration write cycle on the PCI bus as described below.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 75% of the total text.

Technique for Gaining Indefinite Access to Peripheral Component Interconnect*
Bus Resource

      Disclosed is a technique which enables a PCI bus master to gain
indefinite access to the multiplexed address/data lines of the PCI
local bus.  This is accomplished by initiating a configuration write
cycle on the PCI bus as described below.

      In a system which utilizes the PCI local bus, it may be
desirable to use the multiplexed address/data lines for more than
strictly PCI compliant transactions.  Examples include direct
connection of ROM, and intra-chipset communication.  In the event
that the device requiring access is not the PCI arbiter, a mechanism
is required to secure the PCI local bus in a manner which neither
violates the existing PCI specification, nor triggers an error
condition in any of the other PCI bus slaves logically connected to
the PCI bus.

The mechanism is described below:

Master arbitrates for the bus by asserting it's PCI REQ# line.

Master waits for PCI arbiter to assert it's PCI GNT# line.

      Once a qualified PCI bus grant is detected the master initiates
a 'Type 0' configuration write cycle, but does not assert any IDSEL
lines (FRAME# asserted, C/BE# lines = '1011', PCI_AD lines are all
driven to zero.

On the next clock, the master negates the FRAME# line, and asserts
the IRDY# line.

      The PCI_AD lines are now available to the master as long as
IRDY# remains assertive.  The master is still responsible for driving
the co...