Browse Prior Art Database

Automatic Generator of Aussim Testcase from Stocs

IP.com Disclosure Number: IPCOM000117588D
Original Publication Date: 1996-Apr-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 81K

Publishing Venue

IBM

Related People

Lasota, P: AUTHOR [+2]

Abstract

Aussim testcases are very long and time consuming to write. In order to test our chip with an adequate amount of data to be confident enough to release it, required running simulation for over one million simulation time units would require over 400,000 lines of testcase code to stimulate the very complicated interfaces to our chip.

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Automatic Generator of Aussim Testcase from Stocs

      Aussim testcases are very long and time consuming to write.  In
order to test our chip with an adequate amount of data to be
confident enough to release it, required running simulation for over
one million simulation time units would require over 400,000 lines of
testcase code to stimulate the very complicated interfaces to our
chip.

      Whenever the chip is changed, with bug fixes or new function,
the stimulus and the "expect"s can change.  Some changes can
propagate through simulation time, causing your entire testcase to
change.

      The solution is to have the STOCS simulation driver
automatically generate the Aussim testcase.

      Another logic simulation platform called STOCS is used prior to
Aussim.  STOCS models are generated from VHDL, a RTL level language.
Aussim models are generated from BDLS, a gate level language that is
synthesized from the VHDL.  The stimulus for a STOCS model is a C
program, called the driver.  Compared to most testcase languages, C
is much easier to write in.  STOCS testcases also run much faster
than Aussim.

      The sim plan called for running many testcases on the
functional paths in our chip using STOCS.  Then, later in the
development cycle, run Aussim to test the physical aspects, like
scanning, power on reset, interface timings and the like.  There was
also the requirement that one functional test similar to the one run
in STOCS would be run with all the delays to verify the timing in
functional mode.  This was potentially a very difficult test to
write.

In order to generate an Aussim testcase, the STOCS driver program has
to:
  o  Open the file
  o  Generate the "proc" statement and a few other preliminary
      statements.
  o  Generate the "set" and "expect" statements of the test.
  o  Generate the "tgo" statements to advance simulation time.
  o  Generate the "endproc" statement and close the file.

      Opening and closing the file can be done by the driver at the
same time of opening the other data files for the testcase.
Generating the "proc", "endproc" and other preliminary statements can
be done at the same time.

      The i...