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Browse Prior Art Database

Power Saving Latch

IP.com Disclosure Number: IPCOM000117590D
Original Publication Date: 1996-Apr-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Ciraula, M: AUTHOR [+2]

Abstract

Disclosed is a latch which can be used in conjunction with dynamic logic to significantly reduce average power dissipation.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Power Saving Latch

      Disclosed is a latch which can be used in conjunction with
dynamic logic to significantly reduce average power dissipation.

      Dynamic logic dissipates power every time it switches.  In
situations where both the true and complement cones of logic follow a
latch, one of the dynamic logic cones will always dissipate power.

      The Figure shows the embodiment of a latch which has an
additional logic state, which does not require either of the
subsequent logic cones to dissipate power.  The latch is integrated
with a 2:1 mux, and when neither of the selects are activated in a
cycle, both the "true" and "complement" outputs stay low.  As a
result, both cones of logic following the latch remain inactive.
Many variations of this theme are possible, including standalone
latches or integration of the latch with many other logic gates.

      The described technique is especially useful for large macros
such as multipliers which rely on the use of both true and complement
logic.  With prior art, a multiplier directly fed from a latch would
evaluate every cycle even when the result of the multiply operation
would not be required.  This invention provides a convenient way to
eliminate the unnecessary evaluations thus reducing average power.