Browse Prior Art Database

Power Managed Second-Level Cache Control

IP.com Disclosure Number: IPCOM000117595D
Original Publication Date: 1996-Apr-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 4 page(s) / 114K

Publishing Venue

IBM

Related People

Bocchino, TA: AUTHOR [+4]

Abstract

Disclosed is a method for electrically isolating a second-level (L2) cache from the processor local bus. For applications such as notebook computing, where power consumption is a major concern when running off the battery, this can significantly reduce total system power consumption. The L2 can be connected and utilized when AC power is available, and dynamically isolated when the system is operating from battery power.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Power Managed Second-Level Cache Control

      Disclosed is a method for electrically isolating a second-level
(L2) cache from the processor local bus.  For applications such as
notebook computing, where power consumption is a major concern when
running off the battery, this can significantly reduce total system
power consumption.  The L2 can be connected and utilized when AC
power is available, and dynamically isolated when the system is
operating from  battery power.

      Existing notebook computers have a performance drawback because
many do not have a second-level (also referred to as "level-two" or
"L2") cache for the processor.  The primary hindrance to having an L2
cache is the fact that the power it requires exceeds what a notebook
battery is designed to supply.  The addition of an L2 cache would
consume large amounts of power and prematurely drain the battery.

      A significant marketing advantage would be realized if a
second-level cache could be designed to consume an extremely low
amount of power when the system is running on battery power.  The
performance increase would provide "desktop" speeds in a notebook
form factor -- without compromising battery life.

      A method was devised to disable the L2 cache, and thus have it
consume almost no power, while the system is battery powered.  The
solution involves both hardware and software to disable the power and
isolate (or "float") the L2 cache from the processor local bus.  The
primary concern in devising this solution was for the L2 cache to be
made totally invisible to the processor.  Simply powering down the
modules would not work because the local bus would still be connected
to the inputs of the modules, causing them to partially power up (and
potentially damaging the components).  A method was necessary not
only to disable power to the modules, but also to electrically
disconnect the modules from the bus.

      As shown in Fig. 1, a series of analog switches was used
(termed "BUS SWITCHES") to disconnect the modules from the local bus.
Power is removed from the modules in normal power management fashion
using a power FET gated by a control signal.  The invention comprises
the following elements:
  1.  POWER SEQUENCER / CONTROL LOGIC
        Provides signals to control power and connection to the L2
       cache.  One latched signal controls the cache power supply by
       switching a power FET on or off.  The other signal controls
the
       state of the bus switch, which determines whether the L2 cache
 ...