Browse Prior Art Database

Low Power Set Associative Cache Memory

IP.com Disclosure Number: IPCOM000117622D
Original Publication Date: 1996-Apr-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Katayama, Y: AUTHOR [+2]

Abstract

Disclosed is a memory architecture of a set associative cache memory to lower the power consumption of the cache memory system when multiple sets of the memory arrays are used. This method is in particular effective when DRAMs are used for a cache memory.

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Low Power Set Associative Cache Memory

      Disclosed is a memory architecture of a set associative cache
memory to lower the power consumption of the cache memory system when
multiple sets of the memory arrays are used.  This method is in
particular effective when DRAMs are used for a cache memory.

      Fig. 1 shows an example of the conventional set associative
cache memory.  Set associative scheme have an advantage over much
simpler direct mapping scheme in terms of the hit ratio for a fixed
amount of memory by dividing the memory into multiple sets.  The
late-select option is often used to hide the address comparison time
between incoming address and the tag address behind the memory access
time.  However, the late-select scheme increase the power consumption
as the number of sets increase.

      On the other hand, in the present invention shown in Fig. 2, a
single set of the memory array is used instead of the multiple sets
of arrays.  The multiple sets are located in different column address
locations of the single memory array.  The late select is done by
selecting the data by the column address bit(s).

      This method is quite effective when DRAM array is used for a
cache memory.  This is because typically, the page size (i.e., the
number of bitline pairs on the wordline) is much larger than the
number of I/O's from the array.  For example, the page size is
512-2048 in the  current DRAM while the number of I/O's is typically
32-64.