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Detection of Interface Synchronization Problems

IP.com Disclosure Number: IPCOM000117629D
Original Publication Date: 1996-Apr-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Engel, Y: AUTHOR [+3]

Abstract

Many applications include an "on chip" interface between two clock domains with no correlation between the two clock signals. For example: Two signals (A & B) are generated by two different latches driven by the same clocking scheme. A & B feed an AND gate which feeds a latch driven by a different clock scheme. Ideally, A & B will switch simultaneously. In reality, there may be a small difference between the switching times of both signals. This difference may be caused by clock skew or by a loading difference between the latches generating A & B. Suppose A changed from "1" to "0" while B changed from "0" to "1". If a timing difference does exist between A & B, there might be a "1" spike on the AND's output. This spike might be latched by the latch sinking the AND. Such "spike sampling" error is very hard to detect.

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Detection of Interface Synchronization Problems

      Many applications include an "on chip" interface between two
clock domains with no correlation between the two clock signals.  For
example: Two signals (A & B) are generated by two different latches
driven by the same clocking scheme.  A & B feed an AND gate which
feeds a latch driven by a different clock scheme.  Ideally, A & B
will switch simultaneously.  In reality, there may be a small
difference between the switching times of both signals.  This
difference may be caused by clock skew or by a loading difference
between the latches generating A & B.  Suppose A changed from "1" to
"0" while B changed from "0" to  "1".  If a timing difference does
exist between A & B, there might be a "1" spike on the AND's output.
This spike might be latched by the latch sinking the AND.  Such
"spike sampling" error is very hard to detect.  Static timing
analysis does not apply across the asynchronous interface since there
is no relation between both clocking schemes.  High-level
(delay-less) simulation environments fail to detect such asynchronous
problems because they assume that A & B will switch simultaneously.

      By inserting "artificial" random delay elements across the
asynchronous boundary, the "ideal" delay-less simulation environment
will be exposed to any potential synchronization problem.  In the
above example, two such random delay elements will be placed by the
simulation environment between A and...