Browse Prior Art Database

Multiword Direct Memory Access Integrated Drive Electronics Hogpen

IP.com Disclosure Number: IPCOM000117633D
Original Publication Date: 1996-Apr-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 4 page(s) / 197K

Publishing Venue

IBM

Related People

Bland, PM: AUTHOR [+6]

Abstract

Disclosed is a method which solves the problem of sharing system bus bandwidth between the Industry Standard Architecture (ISA) bus, which may include non-preemptive Input/Output (I/O) such as enhanced Integrated Drive Electronics (IDE) devices that support Multiword Direct Memory Access (DMA) transfers, and the Peripheral Component Interconnect (PCI) bus. The system that is described in this article is a PowerPC* based personal computer that has a PCI bus and ISA bus which supports the connection of enhanced IDE devices on the ISA bus using slave DMA via a system DMA controller integrated into the PCI-to-ISA bridge chip. Data transfers employ the system DMA controller's Type-F demand mode (5.55 MB/sec), and IDE's Multiword DMA protocol.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 34% of the total text.

Multiword Direct Memory Access Integrated Drive Electronics Hogpen

      Disclosed is a method which solves the problem of sharing
system bus bandwidth between the Industry Standard Architecture (ISA)
bus, which may include non-preemptive Input/Output (I/O) such as
enhanced Integrated Drive Electronics (IDE) devices that support
Multiword Direct Memory Access (DMA) transfers, and the Peripheral
Component Interconnect (PCI) bus.  The system that is described in
this article is a PowerPC* based personal computer that has a PCI bus
and ISA bus which supports the connection of enhanced IDE devices on
the ISA bus using slave DMA via a system DMA controller integrated
into the PCI-to-ISA bridge chip.  Data transfers employ the system
DMA controller's Type-F demand mode (5.55 MB/sec), and IDE's
Multiword DMA protocol.

      Programmed Input/Output (PIO) transfers performed by the host
Central Processor Unit (CPU) are the traditional method used to move
IDE data.  Historically, the PC AT* hard disk controller used PIO
data transfers because the CPU's PIO speed was much greater than the
transfer speed of the DMA controller.  PIO transfers are based on a
two cycle transfer by the CPU.  During an IDE read, the CPU will
perform an I/O read cycle and then a Memory Write cycle.  During an
IDE write, the CPU will perform a Memory Read cycle and then an I/O
Write cycle.  The CPU is tied up during the entire data transfer,
thus increasing CPU utilization.  As IDE has evolved from the
original PC AT hard disk subsystem, faster DMA solutions have been
defined, however the majority of implementations still support PIO
data transfers.  This approach is acceptable for computer systems
that run under a single-threaded, single-tasking operating system,
such as MS-DOS** and Windows**.  In a single-tasking O/S the CPU will
dispatch a job, such as reading a file, and will then wait idle until
the job has been completed.

      The performance tradeoff of the throughput for the hard disk
versus the CPU's utilization must be balanced when a computer system
runs under a multi-tasking operating system, such as Windows/NT**,
OS/2 Warp*, and AIX*.  In a multi-tasking O/S, the CPU will dispatch
several jobs at once, scheduling them in order of priority, and
completing execution of each job with a time-sharing algorithm.  This
type of O/S can better utilize the performance of the CPU, and
subsequently a system's overall performance will increase if tasks
such as data transfers to an IDE hard disk are performed by DMA.

      The IDE standard supports both Singleword DMA and Multiword
DMA data transfers.  The Singleword DMA protocol is based on a DMA
REQuest/DMA ACKnowledgement handshake for each data transfer, while
the Multiword DMA protocol is based on the DMA REQuest being held
active while data is available, thus allowing the DMA ACKnowledge to
control data to be transferred in a burst sequence.  Multiword DMA
offers greater transfer through...