Browse Prior Art Database

Row Address Strobe/Column Address Strobe Configuration for Write-Back Cache System

IP.com Disclosure Number: IPCOM000117636D
Original Publication Date: 1996-Apr-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Fujita, N: AUTHOR [+3]

Abstract

Disclosed is a memory controller that is installable into a computer system having write back cache memory. The memory controller receives an address that a Central Processing Unit (CPU) issues. The memory addresses are defined as Row Address Strobe (RAS) part and Column Address Strobe (CAS) part. Normally, the memory controller defines a RAS address as higher than a CPU address and defines a CAS address as lower than a CPU address, in order to get better performance by making Dynamic Random Access Memory (DRAM) page hit of memory read for a program code mapped to a continuous address range. Fig. 1 shows an example.

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Row Address Strobe/Column Address Strobe Configuration for Write-Back
Cache System

      Disclosed is a memory controller that is installable into a
computer system having write back cache memory.  The memory
controller receives an address that a Central Processing Unit (CPU)
issues.  The memory addresses are defined as Row Address Strobe (RAS)
part and Column  Address Strobe (CAS) part.  Normally, the memory
controller defines a RAS address as higher than a CPU address and
defines a CAS address as lower than a CPU address, in order to get
better performance by making  Dynamic Random Access Memory (DRAM)
page hit of memory read for a program  code mapped to a continuous
address range.  Fig. 1 shows an example.

      The number of RAS/CAS addresses depends on main memory DRAM
configuration.  When a system has cache memory, the main memory
access is reduced because some of the memory access from CPU is
performed by only access of cache memory.  When the system has a
write back type cache system, there is a different type of memory
access.  The memory controller with write back cache needs to treat
these kinds of memory accesses:
  1.  Cache miss read
  2.  Cache miss write
  3.  Cast out for dirty lines and read

Three (3) is the unique type of memory accessing when the system has
the write-back cache memory.  The continuous accessing "cast out" and
"read" has the same cache line address and the different tag address
as shown in Fig. 2.

      Thi...