Browse Prior Art Database

Technique for Using Snooping Bus Microprocessor in a Coherence Memory Hierarchy Director-Based Memory Hierarchy

IP.com Disclosure Number: IPCOM000117668D
Original Publication Date: 1996-Apr-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 58K

Publishing Venue

IBM

Related People

O'Krafka, BW: AUTHOR [+2]

Abstract

Microprocessors designed for use on snooping busses with fixed snoop delay are difficult to use in central-directory based multiprocessors because the bus tenure introduces unacceptable latency for all coherence transactions that must be forwarded to the central directory. This disclosure describes how this limitation can be overcome, with a modest amount of hardware, by disabling snooping for all processors on a bus and forcing all cache coherence activity to be controlled by the central directory.

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Technique for Using Snooping Bus Microprocessor in a Coherence Memory
Hierarchy Director-Based Memory Hierarchy

      Microprocessors designed for use on snooping busses with fixed
snoop delay are difficult to use in central-directory based
multiprocessors because the bus tenure introduces unacceptable
latency for all coherence transactions that must be forwarded to the
central directory.  This disclosure describes how this limitation can
be overcome, with a modest amount of hardware, by disabling snooping
for all processors on a bus and forcing all cache coherence activity
to be controlled by the central directory.

      The principle idea of this disclosure is to disable snooping at
the processors and enforce cache coherence strictly via the central
directory.  This eliminates the need to wait for a snoop response on
a bus.  The Figure shows how snooping processors can be assembled to
disable snooping.  The most significant change is that the shared

"Address-Valid" signal is broken into a collection of separate
"Address-Valid" lines, one per processor.  These separate
"Address-Valid" lines go to a modification of a snooping bus arbiter.
The arbiter is designed so that the "Address-Valid" lines are
asserted only to initiate point-to-point transactions to or from the
interconnection network--they are not used to enable snooping by
adjacent processors.  Since no snooping is allowed, it is possible to
forward a bus transaction to the interconnection network imm...