Browse Prior Art Database

Method to Maintain Pipeline Throughput while Pipeline Depth is Allowed to Vary

IP.com Disclosure Number: IPCOM000117683D
Original Publication Date: 1996-May-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 87K

Publishing Venue

IBM

Related People

Bartling, SC: AUTHOR

Abstract

Microprocessors that contain units with one or more pipeline stages (Floating Point Units, etc.) sometimes require post-processing of a result to complete the operation (such as processing denormalized results for floating point units), or require a variable pipeline depth in general. Typically, this problem is handled by forwarding the result of the unit for further processing, i.e., the operation will require several passes through the functional unit to complete the operation. This adversely effects the pipeline throughput as the unit is not available to execute new operations while the unit is not available to execute new operations while the unit is completing a multi-pass operation or post processing a result. The other alternative is to add additional pipeline stages permanently.

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Method to Maintain Pipeline Throughput while Pipeline Depth is Allowed
to Vary

      Microprocessors that contain units with one or more pipeline
stages (Floating Point Units, etc.) sometimes require post-processing
of a result to complete the operation (such as processing
denormalized results for floating point units), or require a variable
pipeline depth in general.  Typically, this problem is handled by
forwarding the result of the unit for further processing, i.e., the
operation will require several passes through the functional unit to
complete the operation.  This adversely effects the pipeline
throughput as the unit is not available to execute new operations
while the unit is not available to execute new operations while the
unit is completing a multi-pass operation  or post processing a
result.  The other alternative is to add additional pipeline stages
permanently.  This will penalize all instructions and will severely
impact the performance of the microprocessor.

      A novel solution to this problem is to vary the pipeline depth
while providing a multiport storage register (or other memory
element) to accept the completed operation from multiple pipeline
stages.

      For every additional pipeline stage that is variable, an
additional port (or multiple ports, depending on the operation being
performed) is required in the memory element.  This approach is most
practical for a pipeline that has a variable depth limited to one
additional pipeline stage.  This will only require one additional
port in the register file (or rename buffer, or other memory array).

      The additional stage can be added and removed from the pipeline
dynamically and operands can be routed through the additional stage
as required.  The alternative is to route all operands into the
additional pipe stage even if the additional function is not required
and then disable the additional input port to the memory element if
the additional pipe stage was not required.  The alternative proposal
is easier to implement and allows for additional time to decide if
the extra pipe stage is required.

This novel appproach has the following benefits:
  1) This approach allows instructions that do not require
      additional processing to be completed in the shortest possible
      number of pipe stages.
  2) Instructions that require additional processing can be
      completed without requiring to be forwarde...