Browse Prior Art Database

Method for Error Handling in Inline L2 Cache Controller Implementing High Performance Write-Through Operations

IP.com Disclosure Number: IPCOM000117686D
Original Publication Date: 1996-May-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Related People

Boatright, BD: AUTHOR

Abstract

Disclosed is a method for handling errors in an inline L2 cache controller that deeply buffers write-through store operations received from its processor.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 58% of the total text.

Method for Error Handling in Inline L2 Cache Controller Implementing
High Performance Write-Through Operations

      Disclosed is a method for handling errors in an inline L2 cache
controller that deeply buffers write-through store operations
received from its processor.

      Because an inline L2 cache controller is interposed between
its processor and system Input/Output (I/O) devices such as a
graphics display adapter, an undesired decrease in write-through
(non-cachable) store performance occurs.  This decrease in
performance is due to the added latency and overhead of the
write-through store operation propagating through the L2 controller
to its target IO device.  The typical inline L2 cache controller
overcomes the write-through store performance degradation problem by
implementing a deep write-through store buffer.  This buffer is
capable of accepting multiple write-through  store operations from
the controller's processor before those store operations are also
accepted by their target devices.  While this method  does improve
write-through store performance, the ability of a target device to
signal an error condition associated with a specific store operation
is lost.  This loss in error handling ability occurs because  the
inline L2 cache controller has already positively acknowledged the
store operation to the controller's processor which is a required
part of the performance optimization.  In the PowerPC 60x protocol,
the error signal which can...