Browse Prior Art Database

Dynamic Software Programmable Gate Array

IP.com Disclosure Number: IPCOM000117688D
Original Publication Date: 1996-May-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Frankeny, RF: AUTHOR [+3]

Abstract

This invention provides a method for programming gate arrays dynamically. Erasable, programmable, logic devices are traditionally designed using EPROM and EEPROM technologies to provide erasability and programmability. These methods use UV rays or high voltage to provide erasability. This invention describes an alternate mechanism for erasability and programmability that uses a combination of hardware and software and provides increased function and flexibility.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 66% of the total text.

Dynamic Software Programmable Gate Array

      This invention provides a method for programming gate arrays
dynamically.  Erasable, programmable, logic devices are traditionally
designed using EPROM and EEPROM technologies to provide erasability
and programmability.  These methods use UV rays or high voltage to
provide erasability.  This invention describes an alternate mechanism
for erasability and programmability that uses a combination of
hardware and software and provides increased function and
flexibility.

Such a device is organized using the following components:

      Logic array: Each logic array element is a "sea-of-gates" that
performs a sum of products function.  Such logic array elements are
the core of all programmable logic devices.  The number of product
terms is a function of the technology.

      Crossbar switch: The crossbar switch is used to dynamically
connect and disconnect the logic arrays implement the specified
function and is unique to this invention.

      Switch control: The crossbar switch is programmable, i.e., the
connectivity is controlled using a program that is implemented with a
set of special communication instructions.  The controller fetches
and decodes the instructions.

      Memory: Some form of read-write memory (SRAM, DRAM, etc.) is
provided to store he program.

      Clock: In a synchronous implementation, the
fetch-decode-execute cycle is controlled by a global clock.  The
crossbar can be re-conf...