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Data-Out Path with Hierarchical Bit-Address Decoding for Pipeline Arrays

IP.com Disclosure Number: IPCOM000117689D
Original Publication Date: 1996-May-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 4 page(s) / 127K

Publishing Venue

IBM

Related People

Wendel, D: AUTHOR [+2]

Abstract

Disclosed is a circuit concept for the data-out path of Static Random Access Memory (SRAM) arrays with hierarchical bit decoding and pipeline structure, where fast access time is achieved by precharging the common data-line after blocking the input of the pipeline latch, and where the data-valid time is increased by enabling the input of the pipeline latch practically at the same time new data switches the common data-line. Contrary to conventional approaches, the timing of the precharge operation and the timing of the input gate of the pipeline latch are not defined by signals derived from the memory array clock. Instead, the precharge circuit and the input gate of the pipeline latch are controlled by the 'Set Sense Amplifier' and the 'Restore Sense Amplifier' signals.

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Data-Out Path with Hierarchical Bit-Address Decoding for Pipeline
Arrays

      Disclosed is a circuit concept for the data-out path of Static
Random Access Memory (SRAM) arrays with hierarchical bit decoding and
pipeline structure, where fast access time is achieved by precharging
the common data-line after blocking the input of the pipeline latch,
and where the data-valid time is increased by enabling the input of
the pipeline latch practically at the same time new data switches the
common data-line.  Contrary to conventional approaches, the timing of
the precharge operation and the timing of the input gate of the
pipeline latch are not defined by signals derived from the memory
array clock.  Instead, the precharge circuit and the input gate of
the pipeline latch are controlled by the 'Set Sense Amplifier' and
the 'Restore Sense Amplifier' signals.  Due to the direct dependency
of the 'Sense' signal on those two signals, it is possible to achieve
maximum data-valid time without sacrificing access time.  The new
design features fast data-access time in conjunction with maximum
possible data-out-valid time across cycle boundaries, the latter
without loss in access performance.

      According to pipeline strategy, the clock frequency of a
synchronous Random Access Memory (RAM) can be increased by
introducing more pipeline stages.  In a conventional pipeline RAM,
register latches are placed at the word decoder and the output of the
sense amplifier.  In addition, depending on the data-out width,
different levels of bit-decoding can be included in this path.  Since
this is the path with the longest delay, the cycle time of the memory
array can only be decreased if the delay through this path is
reduced.

      Besides a short access time it is a frequent requirement that
the data latched in the pipeline register which is placed in the
data-path behind the sense-amp has to stay valid for a maximum
possible time.  This time may well extend into the following cycle up
to the point new data is available at the output of the sense-amp.
For instance, if the data on the internal data-bus DBI (Fig. 1) is
controlled by signals coming from a source not located on the same
chip (e.g., Late-Select is on another chip, or DBI is connected
off-chip) an increase in data-valid time may be necessary to
compensate for lack of tracking.

      Fig. 1 shows part of a RAM organization including the data-path
from bit-line to internal data-bus DBI at the output of a pipeline
latch.  In the illustrated case, which serves as an example for the
more general applicability of the proposed concept, each sense-amp is
linked to a group of four bit-switches, each bit-switch connecting
the sense-amp with one bit-line pair.  Depending on the bit-addresses
one out of the four bit-select lines BS0...BS3 is swit...