Browse Prior Art Database

Method to Determine a Lead Processor in a Symmetric Multi-Processor System

IP.com Disclosure Number: IPCOM000117691D
Original Publication Date: 1996-May-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Kaiser, J: AUTHOR [+2]

Abstract

Disclosed is a method to pick a lead or master processor in a Symmetric Multi-Processor (SMP) system when all processors are initialized (powered on) at the same time.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 81% of the total text.

Method to Determine a Lead Processor in a Symmetric Multi-Processor
System

      Disclosed is a method to pick a lead or master processor in a
Symmetric Multi-Processor (SMP) system when all processors are
initialized (powered on) at the same time.

      A system must be initialized by a processor in order to set up
(and possibly test) memory and Input/Output (I/O) devices before the
IPL process can begin.  In addition, this initialization or testing
should only be performed once by the lead processor.

      Since all processors are initialized at the same time, each is
capable of assuming this lead role.  This is desirable in case one or
more becomes defective, the system can still be initialized and
operate even though at a lower level of performance.

      The method disclosed uses a facility built into the SMP memory
controller which is called a "first access switch".  It is a readable
register containing a read only bit which returns one value (e.g., 0)
the first time it is read since power on and another (e.g., 1) each
time thereafter.

      The lead or master processor then is the processor who reads
this facility and gets the "first accessed value".  All processors
who read this facility at a later time receive the alternate value,
and become slave processors.  The slave processors then wait on an
action by the master to tell them that the system has been
initialized.  This can be another facility in the memory controller,
or a semaphor...