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Browse Prior Art Database

Performance Measurement Circuit

IP.com Disclosure Number: IPCOM000117697D
Original Publication Date: 1996-May-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 78K

Publishing Venue

IBM

Related People

Thoma, NG: AUTHOR

Abstract

The problem solved by this disclosure is to provide an accurate means to measure a delay element on a chip without the use of special instrumentation which is not always available.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Performance Measurement Circuit

      The problem solved by this disclosure is to provide an accurate
means to measure a delay element on a chip without the use of special
instrumentation which is not always available.

      The circuit could be used to measure a delay element in the
clock circuitry of a modern microprocessor chip or another
application would be to measure to delay of a test inverter chain
commonly used of chips to quantify the speed of the semiconductor
process.  Current art is to place a chain of inverters on the chip
and connect it in a loop configuration to create an oscillator whose
frequency is then measured with a frequency counter to determine the
speed of the process for general characterization, manufacturing
tracking and quality control, and as a means to sort product into
speed buckets for sale where price is a function of performance.  A
frequency counter is not usually available as part of the tester that
is used to test wafers and packaged chips.  This test, if done, is
done in a special lab.

      This disclosure allows such a measurement to be performed as
part of the manufacturing tester in a digital fashion using the
conventional scan in/scan out latch chains.  In similar fashion, the
delay can now be measured in the system in the customer's office
under control of the Bring Up Processor (BUP) using the same scan
in/scan out mechanism.

      The performance measurement circuit is shown in the Figure.  A
chain of non-inverting circuits is shown as S1 S2 S3 S4 ...Sn.  This
chain may be inverting circuits as well but to simplify the
explanation we will consider them to be non-inverting circuits.  The
chain is designed to provide a means to measure the semiconductor
process speed on an individual chip basis since the speed varies
considerably from chip to chip.  The number of circuits in the chain
is made sufficiently large t...