Browse Prior Art Database

Exploitation of Multi-Ported Storage Devices for Multi-Bus Chips

IP.com Disclosure Number: IPCOM000117699D
Original Publication Date: 1996-May-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 57K

Publishing Venue

IBM

Related People

Mak, K: AUTHOR [+2]

Abstract

Today's designs often call for multi-bus implementations with multiple independent ports in a single ASIC for high throughput, to better leverage intergration densities available in submicron technologies and to reduce the number of chiploads presented on a high speed source bus. Without careful selection of the bus interface requirements, the multi-bus design can easily jeopardize functionality, performance, and efficient silicon area usage. If the data that comes in from the multiple buses is combined for storage in a common location, unnecessary complexity and potential stalls can arise routing data into and out of the common storage location.

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Exploitation of Multi-Ported Storage Devices for Multi-Bus Chips

      Today's designs often call for multi-bus implementations with
multiple independent ports in a single ASIC for high throughput, to
better leverage intergration densities available in submicron
technologies and to reduce the number of chiploads presented on a
high speed source bus.  Without careful selection of the bus
interface requirements, the multi-bus design can easily jeopardize
functionality, performance, and efficient silicon area usage.  If the
data that comes in from the multiple buses is combined for storage in
a common location, unnecessary complexity and potential stalls can
arise routing data into and out of the common storage location.

      To combat this, multiported arrays (preferably with symmetrical
read write ports) can be used to isolate the different "data
streams".  Once isolated, each can run independently without danger
of corruption by the others.  The only point of convergence is at the
array.  Thus, it is easier to manage the interactions between the
"data streams" which can be distinguished by address.

      An additional benefit of incorporating a multi-port array
design, involves the streamlining of a wide, high speed data bus into
several smaller independent buses.  This is a common design
requirement presented in bus converters or other such bus linking
ASIC's which have been produced by integrating a number of functions.
To handle the high data rate on the sourc...