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Associative Processing Method for Logic Circuit Simulation

IP.com Disclosure Number: IPCOM000117700D
Original Publication Date: 1996-May-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 4 page(s) / 100K

Publishing Venue

IBM

Related People

Rogers, JF: AUTHOR

Abstract

Disclosed is a method for using an Associative Processor (AP) to simulate a unit-delay or rank-order model of a digital circuit while attached as a coprocessor to an engineering workstation. An AP comprises a Content-Addressable Memory (CAM) with maskable, word-parallel search functions, and a set of special registers and row-logic at each storage location of the CAM (Fig. 1).

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Associative Processing Method for Logic Circuit Simulation

      Disclosed is a method for using an Associative Processor (AP)
to simulate a unit-delay or rank-order model of a digital circuit
while attached as a coprocessor to an engineering workstation.  An AP
comprises a Content-Addressable Memory (CAM) with maskable,
word-parallel search functions, and a set of special registers and
row-logic at each  storage location of the CAM (Fig. 1).

      A digital circuit design description is stored in the AP CAM;
the basic storage pattern is shown in Fig. 2.  Each logic gate
occupies a contiguous block of CAM (two or more rows), with each
input to and each output from the gate occupying a separate row of
CAM.  Each internal  circuit signal is represented in the CAM by a
unique index, which the host processor correlates to the circuit
design data base.  The CAM word  stores the signal index and a gate
control field.  The gate control field includes a code for gate
function (AND, OR, XOR, etc.) and a flag  to label the signal as an
input or output.  Also included are flags for  signal polarity and
for identification of the first and last CAM rows of  the gate.  The
present state of the signal (logical 1 or 0) is stored in  a tag bit.
Tag bits are special bits of each CAM word (row) that can be
written independently of the remaining bits of the word.

      To simulate a single clock cycle of the circuit, the hose
computer presents the list of signal indexes of circuit inputs, one
at a time, to the CAM.  Wherever the matching signal index occurs in
a CAM row flagged as a gate "input", the state of the signal (1 or 0)
is stored in the tag field, simultaneously for all occurrences.  When
the list is exhausted, all gates are subsequently computed in
parallel using the row logic, and any newly altered gate output
signals are flagged.  Altered signals are propagated forward through
the circuit model by reading their indices and logical states out of
the CAM individually and presenting them to the CAM as new inputs,...