Browse Prior Art Database

Novel Self-Timed Content Addressable Memory Cell

IP.com Disclosure Number: IPCOM000117704D
Original Publication Date: 1996-May-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 53K

Publishing Venue

IBM

Related People

Dietz, CD: AUTHOR

Abstract

Disclosed is a novel self-timed Content Addressable Memory (CAM) cell which is faster than conventional self-timed CAM cells.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 78% of the total text.

Novel Self-Timed Content Addressable Memory Cell

      Disclosed is a novel self-timed Content Addressable Memory
(CAM) cell which is faster than conventional self-timed CAM cells.

      Fig. 1 shows a typical self-timed CAM cell which minimizes
MATCH line loading.  The bitlines are precharged low and then driven
high, which enables the comparator.  This cell has a large bit-line
capacitance because the bitlines see the capacitance of node i, which
includes the gate loading of each cell's pulldown device.  Also, the
pulldown device can never completely turn 'on' because the voltage at
node i can never rise above (Vdd-Vt).

      Fig. 2 shows another typical self-timed CAM cell.  This cell
minimizes bitline loading, but maximizes MATCH line loading, since it
places four times as much diffusion loading on the MATCH line as the
CAM cell shown in Fig. 1.  This cell may still have large bitline
capacitance, however, because of the large size of the series
pulldown devices.

      Fig. 3A shows the novel self-timed CAM cell.  This cell places
an inverter between node i and the single pulldown device.  This
inverter serves three functions.  First, the inverter allows the
bitlines to be precharged high and then driven low, which is faster
than precharging the bitlines low and then driving them high.
Second, the inverter acts as a buffer, lowering the capacitance on
node i and thus the capacitance seen by the bitlines.  Finally, this
inverter drives the pul...