Browse Prior Art Database

Management of Packets that Cross Asynchronous Boundaries

IP.com Disclosure Number: IPCOM000117708D
Original Publication Date: 1996-May-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Mak, K: AUTHOR [+3]

Abstract

Transmission of packets many bits wide across an asynchronous boundary (each region operates at a different frequency) presents a design challenge to guarantee data integrity and to control the amount of logic dedicated to managing the crossing. Each bit that is sourced on one side of the boundary and received on the other may become metastable or may be overrun with incoming data. Handling these potential problems by double latching or by forms of flow control may severely degrade packet throughput across the asynchronous boundary. Use of double latching may bloat the latch count on the chip to unacceptable levels.

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Management of Packets that Cross Asynchronous Boundaries

      Transmission of packets many bits wide across an asynchronous
boundary (each region operates at a different frequency) presents a
design challenge to guarantee data integrity and to control the
amount of logic dedicated to managing the crossing.  Each bit that is
sourced on one side of the boundary and received on the other may
become metastable or may be overrun with incoming data.  Handling
these potential problems by double latching or by forms of flow
control may severely degrade packet throughput across the
asynchronous boundary.  Use of double latching may bloat the latch
count on the chip to unacceptable levels.

      To avoid all of the problems mentioned above, a storage device
with separate read and write ports is used.  When a packet is to be
transmitted across the asynchronous boundary via the dual ported
storage device, the message and data payload from the packet is
written into the dual ported storage device and the valid bit for the
packet is set but only after the entire payload is in place.  The
valid bit is the only bit of the whole packet that is required to be
managed across the asynchronous boundary.  The valid bit will wake
the packet state machine on the receiving side to process the
incoming packet which is stable in the dual ported storage device and
the possibility of encountering metastability has been reduced.  Only
one bit can be affected by metastability instead the...