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Reduction of Error Responses and Link Error Isolation

IP.com Disclosure Number: IPCOM000117710D
Original Publication Date: 1996-May-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 57K

Publishing Venue

IBM

Related People

Herger, L: AUTHOR [+5]

Abstract

Disclosed is a design to reduce bus error responses and isolate link errors in a remote input/output (I/O) chip set environment.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Reduction of Error Responses and Link Error Isolation

      Disclosed is a design to reduce bus error responses and isolate
link errors in a remote input/output (I/O) chip set environment.

      The 6xx and 6xx-Mx bus have a number of response and status
lines which generate and monitor error conditions such as ASTATXX,
ARESPXX, BUSCHKXX, MACHINE CHECK, and CHECKSTOP.  Collectively, these
signals indicate the status of the bus and its current operations.

      Due to the availability of these system lines, there are a
large number of error conditions which must be responded to and
handled by any device which conforms to this bus architecture.

      In order to simplify and centralize the categorization and
retrieval of the error status for both hardware and software, the
remote I/O chip set has reduced the responses to the errors to a
limited set:
  o  for recoverable errors, or less severe errors, log the error
      information in 6xx/6xx-Mx error register
  o  for recoverable, but more severe errors, issue a machine check
to
      the processor and log the error information.
  o  for remote recoverable errors, the host will issue an interrupt
      to the processor on behalf of the bridge (or remote I/O).

      By reducing the variety of responses to errors, the logic has
been simplified resulting in lower cost, in less risk of defect, and
in faster design cycle time.  The logging activities have also been
adjusted to favor lower cost, less risk and faster desig...