Browse Prior Art Database

On-Chip Performance Monitoring Sharing Rename Registers

IP.com Disclosure Number: IPCOM000117730D
Original Publication Date: 1996-May-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 4 page(s) / 135K

Publishing Venue

IBM

Related People

Levine, FE: AUTHOR [+3]

Abstract

Disclosed is an approach that allows for the sharing of registers that would normally be dedicated to hardware performance monitoring.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 45% of the total text.

On-Chip Performance Monitoring Sharing Rename Registers

      Disclosed is an approach that allows for the sharing of
registers that would normally be dedicated to hardware performance
monitoring.

      Assuming the support defined in the PowerPC 604* RISC
Microprocessor User's Manual, find a way to maximize the utilization
of registers that are used for performance monitoring.

      In order to collect information for performance monitoring, it
is necessary to have various registers or memory elements in order to
store the counted events.  Many times it is difficult to collect
accurate data because many runs of the software may be necessary in
order to get all the needed data.  This is the case if the number of
events to be monitored is greater than the number of available
counters.  By counting information from different runs, one may get
inaccuracies created by system software.  A higher degree of accuracy
may be needed in some cases.  In order to do this, one must use more
counters and count all needed information in one run.  This way the
system has affected all counts equally.  The drawback to this method
is that the hardware needed to support this is has traditionally been
very expensive.

      The Performance Monitor for PowerPC (TM) microprocessors is a
software accessible mechanism intended to provide detailed
information concerning the utilization of PowerPC instruction
execution and storage  control.  The monitor consists of an
implementation dependent number (2-8) 32-bit counters (PMC1, PMC2,
PMC8) to be used to count Processor/Storage performance related
events.

      The Monitor Mode Control Registers (MMCR0, MMCR1) establish
the function of the counters.  The counters and the MMCRn physically
reside on the 6XX chip and are addressable for read or write via
mfspr or mtspr instructions.  Writing to these SPRs is only allowed
in supervisor or privileged state.  Reading from these SPRs may also
be allowed in the problem state.  Reading these counters/registers
does not change their content.

      The Monitor Mode Control Registers (MMCRn) are partitioned into
bit fields that allow for selection of events (signals) to be
recorded (counted).  Selection of allowable combinations of events,
causes the counters to operate concurrently.  The MMCRn includes
controls, such as, counter enable control, counter negative interrupt
control, counter event selection, and counter freeze control.

      The PowerPC microprocessors which support Performance
Monitoring contain an implementation dependent number of events that
can be selected for counting.

      Rename registers are physical memory elements that a
microprocessor uses in order to store temporary results.  There are
more rename registers than architectural registers in today's
microprocessors.  When an instruction is executed out of order it has
its results stored in a rename register.  When the completion unit
decides that the i...