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Efficient Simulation Compute Power with Enhanced Testcase Generation Scheme

IP.com Disclosure Number: IPCOM000117731D
Original Publication Date: 1996-May-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 4 page(s) / 92K

Publishing Venue

IBM

Related People

Jessani, R: AUTHOR [+4]

Abstract

Disclosed is a testcase generation scheme which utilizes a programmable checksum checking facility to test the validity of the microprocessor model during simulation to ensure the correctness of architected registers. This scheme allows the testcases to be simulated by checking the architected registers after a programmable number of instructions/cycles have elapsed and eases the burden on computing resources by not having to carry out a check after every instruction or executing further cycles after a fail has been detected.

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This is the abbreviated version, containing approximately 52% of the total text.

Efficient Simulation Compute Power with Enhanced Testcase Generation
Scheme

      Disclosed is a testcase generation scheme which utilizes a
programmable checksum checking facility to test the validity of the
microprocessor model during simulation to ensure the correctness of
architected registers.  This scheme allows the testcases to be
simulated by checking the architected registers after a programmable
number of instructions/cycles have elapsed and eases the burden on
computing resources by not having to carry out a check after every
instruction or executing further cycles after a fail has been
detected.

      Verification of the microprocessor model is carried out by
simulating architectural verification programs (testcases - generated
by the Random Testcase Pattern Generator (RTPG)) and using a testcase
executor (Rtx) to check on the architected registers and memory
locations by comparing with the values expected by the testcase
itself.  Microprocessor verification involves billions of cycles of
simulation on dedicated queues and machines.  Efficient utilization
of these resources leads to saving wasted simulation cycles.

      This scheme involves pre-defining a checksum space and a
checksum results space.  The checksum space contains the code to be
executed every 100 (or programmable) instructions in the testcase.
The testcase generation includes inserting the checksum code in the
testcase, and the code utilizes the pre-defined checksum results
space to:
  1.  store current architected register values (necessary to
maintain
       machine state) and
  2.  store the final checksum value.

      The architected register saved in the checksum results space
before the execution of the checksum code is loaded back at the end
of the checksum code sequence to maintain machine state.

      The final checksum value saved in the checksum results space at
the end of the checksum code is used to ensure the validity of the
testcase execution.

      The Figure shows the memory graph defining the non-intersecting
instruction, data, checksum code and checksum results spaces.

      The checksum sequence (for the GPRs) involves saving the
current value of GPR0, adding all GPRs that have changed values in
the 100 instructions executed (up to a maximum of 32 adds) and
storing the checksum value in the results space.

Checksum sequence:
  stw G0, te...