Browse Prior Art Database

Channel Command Word Fetching and Validation Hardware

IP.com Disclosure Number: IPCOM000117732D
Original Publication Date: 1996-May-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 4 page(s) / 99K

Publishing Venue

IBM

Related People

Dieffenderfer, JN: AUTHOR [+4]

Abstract

Disclosed is a VLSI system bus adapter chip which has hardware assist for Channel Command Word (CCW) fetching and validation. This chip is used on all models of ES/9370 and will be used on future products.

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This is the abbreviated version, containing approximately 52% of the total text.

Channel Command Word Fetching and Validation Hardware

      Disclosed is a VLSI system bus adapter chip which has hardware
assist for Channel Command Word (CCW) fetching and validation.  This
chip is used on all models of ES/9370 and will be used on future
products.

      The 6010 controller currently used on the 9370 system uses a
system bus adapter chip which provides an interface between the IBM*
system bus and the Motorola 68K bus.  The original system bus has two
programmable DMA ports.  Port 1 of the original chip was used to
fetch CCW's as well as DMA transfers.  If port 1 was busy doing a
long data transfer, requests for CCW fetching were queued up in
software resulting in loss of performance.  The original chip had no
provision for CCW validation.  CCW validation was done completely in
software.

      The method described below introduces the addition of a third
port and a CCW validation state machine in a new system bus adapter.
The new hardware decreases time lost in queueing of requests for CCW
fetching and reduces cod for CCW validation.

      The Figure shows the data flow of the hardware developed to
speed the fetching and validation of CCW's and IDAW's.  Ports 0 and 1
are not shown in the Figure for clarity.  The two internal arrays for
port 2 are imbedded arrays.  The arrays are 18 bits wide and 32 words
long.  The arrays are dynamically configured to hold exactly one
system bus 1 line length of data.  The outputs of the arrays feed
four 16 bit registers 4 and a mux 7 to the microprocessor data bus 8.
There is also a status register 5 associated with port 2.  The status
register provides system bus status for port 2 and a port 2 active
bit.  The 16 bit registers which are fed from the arrays are called
the Checking Registers 4 and they hold the CCW's/IDAW's to be
validated.  The Checking Registers feed CCW/IDAW validation logic 6
The outputs of the validation logic are available to the
microprocessor via an address decode within the new chip.  The
Checking Registers are not available to the microprocessor.  The CCW
Sequencer 3 is a simple four state machine which controls the loading
of the Checking Registers.

      CCW or IDAW fetching is accomplished by loa...