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Integer Divisible Frequency Divider with Symmetric Outputs

IP.com Disclosure Number: IPCOM000117740D
Original Publication Date: 1996-May-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 66K

Publishing Venue

IBM

Related People

Nguyen, T: AUTHOR [+2]

Abstract

Frequency dividers are common but this circuit provides a frequency divider that is programmable for any integer divider ratio nad at the same time provides an output signal that is symmetrical (50% duty cycle).

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Integer Divisible Frequency Divider with Symmetric Outputs

      Frequency dividers are common but this circuit provides a
frequency divider that is programmable for any integer divider ratio
nad at the same time provides an output signal that is symmetrical
(50% duty cycle).

      The resulting waveform is useful in many applications.  The
specific need leading to this disclosure was the requirement for such
a capability in the 630 microprocessor clock design.

      The invention is explained with the help of Fig. 1.  The L1/L2
latch pairs are all initially set to a zero logical state.  The
details of the reset circuitry is not shown in Fig. 1 to simplify the
Figure.

      Each latch pair feeds both the next L1 input and a mux.  The
mux may take the form of a tri-state on chip driver where only one
driver is activated at a time or it may take the more common form of
1 of 2, 1 of 4, or 1 of 8, select circuits but whatever the form, the
idea is to select one and only one of the latch pair outputs for
feedback to the first latch pair input through an inverter.  The
Figure shows control signal such as "divide by 1" which determines
the frequency division ratio.  Three stages are shown in the Figure
but this arrangement could be continued further, i.e., through N
stages for a divide by N ratio.

      To understand the operation assume we want to divide by 1.  All
latches are set to zero.  The double frequency clocks are applied,
i.e., L1CLK and L...