Browse Prior Art Database

Window Matching State Machine for Bus Interface Design

IP.com Disclosure Number: IPCOM000117741D
Original Publication Date: 1996-May-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Arimilli, RK: AUTHOR [+2]

Abstract

The 6XX system bus is a non-blocking, high data throughput rate, highly capable and robust for supporting a wide range of system designs, such as large multi-processors and Input/Output (I/O) intensive system. The design challenge involved for this kind of demanding system bus environment has been somewhat reduced with a built in response period, allowing more time for the 6XX bus participants to respond accurately to one of many outstanding address requests which involves coherency checking and status checking.

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Window Matching State Machine for Bus Interface Design

      The 6XX system bus is a non-blocking, high data throughput
rate, highly capable and robust for supporting a wide range of system
designs, such as large multi-processors and Input/Output (I/O)
intensive system.  The design challenge involved for this kind of
demanding system bus environment has been somewhat reduced with a
built in response period, allowing more time for the 6XX bus
participants to respond accurately to one of many outstanding address
requests which involves coherency checking and status checking.  This
so call response period for address response is "TLAR", the process
itself is highly complex with the response period that can have a
value of 4 to 16, in which up to 8 address operations can be issued
if the value is set to 16, and the address status and address
responses do not have Identification (ID) tag to identify which set
of status and responses is for which address operation.

      To minimize the complexities in the design of the TLAR state
machine that can track up to 8 outstanding operations, a conveyor
belt of shift registers is used to shift tagged incoming operations
through the shift registers as they are received, then the address
status is pickup at the appropriate time so that the status is now
identifiable with the address request.  Finally, a multiplexor is
used to select a window in time based on the TLAR value, to pick out
the tagged request and the address status...