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Multi-Ratio Prescaler for Frequency Synthesis

IP.com Disclosure Number: IPCOM000117747D
Original Publication Date: 1996-May-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Girard, P: AUTHOR [+2]

Abstract

Disclosed is a method of building a frequency prescaler with a large number of division ratios in a simple and efficient manner. As can be seen in the Figure, the input signal, IN, which has to be frequency divided is first divided by a 2 modulus (4 or 5) divider, M1, whose modulus is selected by the output of the NOR gate. The output of M1 is frequency divided by identical prescalers M2 and M3, with the same dividing ratios, and who are independently selected by control inputs MC2 and MC3. The object of M2 and M3 is to obtain other division ratios and further frequency scaling. The object of M1 combined with the NOR gate is to be able to obtain N and N+1 ratios.

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Multi-Ratio Prescaler for Frequency Synthesis

      Disclosed is a method of building a frequency prescaler with a
large number of division ratios in a simple and efficient manner.  As
can be seen in the Figure, the input signal, IN, which has to be
frequency divided is first divided by a 2 modulus (4 or 5) divider,
M1, whose modulus is selected by the output of the NOR gate.  The
output of M1 is frequency divided by identical prescalers M2 and M3,
with the same dividing ratios, and who are independently selected by
control inputs MC2 and MC3.  The object of M2 and M3 is to obtain
other division ratios and further frequency scaling.  The object of
M1 combined with the NOR gate is to be able to obtain N and N+1
ratios.

      As implemented in the Figure, the new circuit is able to
synthesize 6 different ratios correctly spaced, and listed in the
Table.  When used in a frequency synthesis PLL, this prescaler
enables to lower the minimum ratio from which all integer ratios are
synthesizable to 1441 compared to 4032 for a regular 64, 65
prescaler.  This is a 2.8 X improvement.  Moreover, when very high
dividing ratios are required for the PLL, this prescaler which have
higher ratios (100 and 101), can save 1 to 2 bits to the companion
counter, which is more easily implemented and which can go faster.

      This solution offers, hence, superior performance only by using
simple building blocks which can be easily migrated from one
technology to the other.

Table  Prescaler R...