Browse Prior Art Database

Dynamic Power Control for Solid State Storage

IP.com Disclosure Number: IPCOM000117749D
Original Publication Date: 1996-May-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Sakaue, Y: AUTHOR

Abstract

Disclosed is a semiconductor storage device which can optimize its power consumption by measuring the access speed of a host system. The device counts the number of the wait pulses asserted by host interface modules during the time of data transfer, and increases or decreases the operation clock frequency until the number of the wait pulses becomes within a predetermined range of value.

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Dynamic Power Control for Solid State Storage

      Disclosed is a semiconductor storage device which can optimize
its power consumption by measuring the access speed of a host system.
The device counts the number of the wait pulses asserted by host
interface modules during the time of data transfer, and increases or
decreases the operation clock frequency until the number of the wait
pulses becomes within a predetermined range of value.

      The Figure shows a block diagram that embodies the present
invention, and a timing chart that shows the operation thereof.  The
host interface module has a circuit to count the number of the wait
pulse during the time of data transfer and a register to store the
number which can be accessed by a microprocessor.

      The operation clock is controlled by the clock divider.  The
clock divider reduces the output clock frequency to that of the input
clock frequency divided by a number, which is set by the
microprocessor.

      The microprocessor first reads the number of the wait pulse
through the register of the host interface module, and then changes a
divisor value set in the clock divider.  For example, when the number
of the wait pulses is too large, which means that the operation clock
is too slow and so the Input/Output (I/O) performance at system level
is degraded, the microprocessor sets the divisor value to half the
current value.  The microprocessor continues to reduce the divisor
value until the number o...