Browse Prior Art Database

Programmable Cacheable Memory

IP.com Disclosure Number: IPCOM000117753D
Original Publication Date: 1996-May-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Pham, D: AUTHOR [+2]

Abstract

In many micro-processor systems, large addresses are architected. As many as 64 bits of address are implemented. This presents a problem in Cache designs. Part of the address (the Tag) must be kept in the Cache Directory. The size of the address makes the cache directory very large. One solution to this problem is to identify the cacheable range of memory externally to the directory and truncate the amount of address needed for the tag. Additionally, this external range detection will improve system performance since devices and processes that use non-cachable memory, will not require cache look-up.

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Programmable Cacheable Memory

      In many micro-processor systems, large addresses are
architected.  As many as 64 bits of address are implemented.  This
presents a problem in Cache designs.  Part of the address (the Tag)
must be kept in the Cache Directory.  The size of the address makes
the cache directory very large.  One solution to this problem is to
identify the cacheable range of memory externally to the directory
and truncate the amount of address needed for the tag.  Additionally,
this external range detection will improve system performance since
devices and processes that use non-cachable memory, will not require
cache look-up.

      The proposed solution is to utilize one or more address bits to
define a range of cacheable memory.  In the example, the top three
bits are used to define a range of cacheable memory.  A separate
register (that could be a special purpose register as an example)
holds three bits.  Only address who's top three bits (0:2) are
identical with the contents of the separate register are cacheable.

Now the Cache Directory doesn't have to have bits 0:2 as part of the
Tag so the RAM size needed for the directory is smaller.

      Refer to the Figure.  In the example described, the special
register is called a "Cacheable address register" (CAB).  A
Comparator marks a memory address as cacheable (Valid) when the CAB
is identical with the MSB (0:2).