Browse Prior Art Database

Coexistence of Multiple Interrupt Routers on One Processor Bus

IP.com Disclosure Number: IPCOM000117757D
Original Publication Date: 1996-May-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 4 page(s) / 79K

Publishing Venue

IBM

Related People

Bronson, TC: AUTHOR [+2]

Abstract

Disclosed is a method to allow multiple PowerPC* interrupt routers, as defined in the "RISC System/6000* PowerPC System Architecture" to work together on the same processor bus.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 53% of the total text.

Coexistence of Multiple Interrupt Routers on One Processor Bus

      Disclosed is a method to allow multiple PowerPC* interrupt
routers, as defined in the "RISC System/6000* PowerPC System
Architecture" to work together on the same processor bus.

      Fig. 1 shows a multiprocessor system where the interrupt
routing task is shared by multiple interrupt routers, each of which
is contained on a separate multi-function chip.

      In this system, all interrupts from local and remotely attached
Bus Unit Controllers (BUCs) are directed to the processor bus where
they take the form of an interrupt command packet.  In addition, all
accesses to the memory mapped interrupt presentation registers are
performed via the processor bus.  Each chip containing an interrupt
router is provided with a means to distinguish which interrupt
commands are targeted for the processors served by that router.  A
special set of configuration registers in each router is used to
establish which processors and which groups (Global servers) of
processors are served by that interrupt router.  This information
allows the chip containing the router to selectively acknowledge
interrupt commands based on processor number or group and to
selectively acknowledge the memory mapped accesses to the interrupt
presentation registers associated with those processors.

      The Processor affinity registers required to allow the
interrupt routing function to be divided between multiple chips are
defined in the following list.  Each interrupt...