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Buried Stud that Eliminates Substrate and Well Contact Requirements

IP.com Disclosure Number: IPCOM000117784D
Original Publication Date: 1996-Jun-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 91K

Publishing Venue

IBM

Related People

Christensen, TA: AUTHOR [+2]

Abstract

Disclosed is a buried stud technique that eliminates the need for nearly all traditional power connections to substrate and n-wells.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Buried Stud that Eliminates Substrate and Well Contact Requirements

      Disclosed is a buried stud technique that eliminates the need
for nearly all traditional power connections to substrate and
n-wells.

      Integrated circuit chip designs are significantly limited by
the requirements for very large numbers of substrate and n-well
connections.  These connections tend to consume relatively large
amounts of the chip silicon area (often in excess of 5%) and even
larger amounts of the first level wiring level (on the order of 10%)
even though that adds no function beyond ensuring proper biasing.
The problems associated with substrate and n-well connections are
even more pronounced in application specific integrated circuits
where a standard library of circuit elements is heavily used.  Both
substrate and well connections must be added into even the smallest
library element (inverters, for instance) to ensure the proper power
biasing is applied.  Multiple connections to a single (continuous)
well are often made well within the area where a single contact would
meet the technology ground rule requirements.  This situation occurs
even more frequently when one examines substrate contacts.

      This method allows for the connection of the substrate and
the wells to the necessary power supplies through contacts that are
required for actual circuit operation; thus, eliminating the silicon
area and metal that was separately dedicated to the connection of
substrate and n-well.  The connections (contacts) that are eliminated
by this invention are replaced by vertical studs between transistor
diffusions (sources and drains) that are connected to the power
supplies for functional reason and the underlying N-well (in the case
of a P channel device diffusion that is tied high) and substrate (in
the case of a N channel device diffusion that is tied low).  This
vertical contact thus eliminates both the silicon area that
traditionally is allocated to the diffusions that are dedicated to
the ohmic connections to the substrate/well as well as all the wires
required to connect these structures.

      The Figure shows the locations of the new s...