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Integrated Control Processor with Shared Queue/Stack Interface and Direct Access Storage Device Control Adapter

IP.com Disclosure Number: IPCOM000117791D
Original Publication Date: 1996-Jun-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 4 page(s) / 135K

Publishing Venue

IBM

Related People

Ouchi, NK: AUTHOR

Abstract

The design of many device adapters require the integration of a control processor with its program storage, a buffer, an interface to the adapter and one or more external interfaces. The design is centered around a high data rate bus arbitration mechanism. A transputer series integrates the processor, interface to external storage, system services, and a set of serial links. The external storage interface is used for multiple purposes: access to program storage, access to the adapter, and access to the buffer used by the adapter. The buffer has two or more source/sinks in addition to the transputer. Thus, much of the adapter design is the development a bus arbitration circuit that connects the transputer, two memories - program and buffer, and two or more interfaces to adapter hardware and bus interfaces.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Integrated Control Processor with Shared Queue/Stack Interface and
Direct Access Storage Device Control Adapter

      The design of many device adapters require the integration
of a control processor with its program storage, a buffer, an
interface to the adapter and one or more external interfaces.  The
design is centered around a high data rate bus arbitration mechanism.
A transputer series integrates the processor, interface to external
storage, system services, and a set of serial links.  The external
storage interface is used for multiple purposes:  access to program
storage, access to the adapter, and access to the buffer used by the
adapter.  The buffer has two or more source/sinks in addition to the
transputer.  Thus, much of the adapter design is the development a
bus arbitration circuit that connects the transputer, two memories -
program and buffer, and two or more interfaces to adapter hardware
and bus interfaces.  This is illustrated in Fig. 1.  In addition, the
main use of the buffer is for FIFO queues that are used to store and
forward, data rate match, etc. large blocks of data.

      Fig. 2 illustrates the integration of current processor, system
services, links, and DRAM interface with a second DRAM interface with
queue/stack pointer logic and an external parallel interface.  This
permits easy developments of adapters since the key bus arbitration
logic is on the integrated chip.  Use of this building block is
illustrated in Fig. 3.  The parallel interface widths may be of
different sizes to fit the applications and also limit the number of
Input/Output (I/O) pins; e.g., the transputer DRAM interface is 36
bits but the shared RAM interface can be 36, 18, or 9 bits as can be
the parallel bus interface.  Fig. 4 illustrates a different division
of the functions over two chips where the transputer chip has a fast
parallel interface with the links removed.  The companion chip has
the same parallel interface with the bus arbitration logic, links,
...