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Browse Prior Art Database

Time Dynamic Logic Precharge Path

IP.com Disclosure Number: IPCOM000117797D
Original Publication Date: 1996-Jun-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Stasiak, DL: AUTHOR

Abstract

Disclosed is a method to time the precharge delay through dynamic circuits.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 78% of the total text.

Time Dynamic Logic Precharge Path

      Disclosed is a method to time the precharge delay through
dynamic circuits.

      A tool called Pathmill* will time a dynamic circuit in the
precharge phase.  The limitation of the tool is it will only time the
first and second precharge nets in a path.  In the Figure, Pathmill
will time from clock (CLK) feeding transistor PS to net "pre2."  The
tool will not continue to net "out2."

      Pathmill recognizes if an evaluate NMOS device is footed.  As
shown in the Figure, a footed device is an NMOS device fed by a clock
that is between ground and the source of an NMOS evaluate device.  In
the foot device for DN, PS93 NFET is a foot device for DN3 but DN2
does not have a foot device.

      Pathmill defaults the length of the precharge path to two
dynamic circuits regardless of the foot devices.  Since Pathmill
understands which transistors are foot devices, the foot devices can
be used to determine the length of the precharge path.

      In the Figure, the first dynamic circuit has a foot device,
PS9.  The timing tool detemines the rise delay of net "pre" and the
fall delay net "out."  The tool sees no foot device for the second
dynamic circuit, so it continues to time the path and determines the
rise delay for net "pre2" and fall delay for "out2."  The tool sees
the third dynamic circuit's foot device, PS93, and determines the
path has ended.

      If the third dynamic circuit had no foot device, th...