Browse Prior Art Database

Device for Error Analysis

IP.com Disclosure Number: IPCOM000117801D
Original Publication Date: 1996-Jun-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 4 page(s) / 77K

Publishing Venue

IBM

Related People

Reichl, L: AUTHOR

Abstract

Device for error analysis in digital electronic appliances, characterized by the fact that both the activation of the test circuit and the display of the error incident are achieved with a single memory element.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 53% of the total text.

Device for Error Analysis

      Device for error analysis in digital electronic appliances,
characterized by the fact that both the activation of the test
circuit and the display of the error incident are achieved with a
single memory element.

      Test circuits in electronic control systems (e.g., computers)
are often required to have the possibility of putting the control
sequence "on hold", in order to store the previous history of the
error and thus facilitate the error analysis.

      When the test circuit is supposed to monitor a certain number
of "N" unrelated error conditions, normally "2xN" memory elements (=
flip-flops) are required in order to have, for each error condition,
the possibility of:
  1.  selecting "pause or no pause" before the start of the
operation.
  2.  registering which of the various error conditions has put the
       system on hold.

      The task is to minimize the number of storage elements required
without restricting the possibilities for error diagnosis.

The solution follows:
  As shown in the Figure, the circuit comprises:
  1.  A register "CHK_DISA_FL(1..N)"
       "N" is the number of error conditions with one bit each for
       each condition "CHK_COND(1..N)"
  2.  Another flip-flop "CHK_STOP_FL" for triggering the system stop
       ("Hold")and
  3.  Combinatory logic.

      The circuit is, therefore, assumed to be "synchronous phased",
in other words the status of the data input of each flip-flop "D" is
taken over in to the flip-flop with the system phase pulse "PHASE"
and is only available in the next system phase at the output "Q", or
as an inverted value at the output "Q".

A further requirement (not shown separately in the diagram) is that:
  o  the register "CHK_DISA_FL(1..N)" must be preloaded before the
      start of operations with a bit pattern "DISABLE(1..N)"
  o  and can be read off again after a system stop.

      Key to diagram:
  OR = OR g...