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Browse Prior Art Database

Backpower Prevention Mechanism

IP.com Disclosure Number: IPCOM000117807D
Original Publication Date: 1996-Jun-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 55K

Publishing Venue

IBM

Related People

Bocchino, TA: AUTHOR [+4]

Abstract

Disclosed is a method for isolating a powered-down subsystem from circuitry that is powered-up, in order to prevent the occurrence of a phenomenon called backpowering, which causes unnecessary power consumption and potential circuitry damage.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Backpower Prevention Mechanism

      Disclosed is a method for isolating a powered-down subsystem
from circuitry that is powered-up, in order to prevent the occurrence
of a phenomenon called backpowering, which causes unnecessary power
consumption and potential circuitry damage.

      Battery power in notebook computers can be less than optimal
due to a phenomenon know as backpowering - a condition where a
powered-down circuit is needlessly and/or accidentally powered-up
through input or output signals that are connected to powered-up
devices.  Therefore, it is desirable to isolate powered-down devices
from powered-up devices.  In notebook as well as green PC designs, it
is important to utilize a low-cost, low-real-estate method for
providing this isolation.

      This design provides a simple solution for preventing
backpowering.  A field effect transistor (FET) is placed inline with
each signal needing isolation, as shown in the Figure.  The drain of
the FET is connected to the powered-up circuit and the source is
connected to the circuit to be powered down.  The gate input would be
turned on (creating a connection between the source and the drain of
the FET) only when the circuit on the source side is powered-up,
otherwise the source and drain are isolated from each other.  When
the gate is turned off, the diode inherent in the FET prevents any
current leakage from the powered-up circuit on the drain side to the
powered-down circuit on the source side.
  For example, to isolate a powered-up CRT from a
powered-down|planar:
       SYSTEM_ON  __________________
  ...