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Browse Prior Art Database

Mechanism for Shared Access of Queues and Stacks through Links and Parallel Bus

IP.com Disclosure Number: IPCOM000117812D
Original Publication Date: 1996-Jun-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 61K

Publishing Venue

IBM

Related People

Ouchi, NK: AUTHOR

Abstract

Disclosed is a mechanism that permits multiple bus attached adapters to use a large RAM as a set of shared queues and stacks. Each queue or stack has a RAM address into which data are written or read. The queue or stack pointers are managed by the mechanism. Thus, the design of adapter's use of the shared queues or stacks is simplified and permits the sharing of queues and stacks in a shared RAM among virtual channels on serial links. Again, the designs of link based adapters that use shared queues and stacks are simplified. The prior art permit the construction of complex systems with simple adapters. This invention relates to a mechanism that permits both a parallel bus and a set of virtual channels and serial links to share a set of queues and stacks in a shared RAM.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 75% of the total text.

Mechanism for Shared Access of Queues and Stacks through Links and
Parallel Bus

      Disclosed is a mechanism that permits multiple bus attached
adapters to use a large RAM as a set of shared queues and stacks.
Each queue or stack has a RAM address into which data are written or
read.  The queue or stack pointers are managed by the mechanism.
Thus, the design of adapter's use of the shared queues or stacks is
simplified and permits the sharing of queues and stacks in a shared
RAM among virtual channels on serial links.  Again, the designs of
link based adapters that use shared queues and stacks are simplified.
The prior art permit the construction of complex systems with simple
adapters.  This invention relates to a mechanism that permits both a
parallel bus and a set of virtual channels and serial links to share
a set of queues and stacks in a shared RAM.  The mechanism has a set
of pointers and hardware for each queue or stack.  Each queue or
stack is assigned an address on the parallel bus interface and a
corresponding virtual channel on the link interface.  The links and
the parallel bus access the RAM thru this mechanism as illustrated in
Fig. 1.  A portion of the RAM can be also accessed a RAM using
addresses other than those assigned to the queues or stacks.  The
design of a storage adapter, as illustrated in Fig. 2, is simplified
in that the automatic data transfer hardware need only fetch or store
to a specific address for a shared queue.  The managem...