Browse Prior Art Database

Clock-Phase Adjustment for Optimizing Data Sampling

IP.com Disclosure Number: IPCOM000117819D
Original Publication Date: 1996-Jun-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Benayoun, A: AUTHOR [+4]

Abstract

Disclosed is a method to center the sampling of data on the rising edge of the clock to avoid side effects like jitter and overshoot on transmission lines. This problem arrives generally with long cabling when data and clock are not in phase. Current transmission standards give no advices except to transmit data and clock with the same cabling in the same direction. This is not always possible nor offered by some standards; i.e., X.21 (single clock). Sometimes the data transmission doesn't work at all or works erroneously depending on the cabling used, the jitter of the clock, or some reinitialization in one of the products interconnected.

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Clock-Phase Adjustment for Optimizing Data Sampling

      Disclosed is a method to center the sampling of data on the
rising edge of the clock to avoid side effects like jitter and
overshoot on transmission lines.  This problem arrives generally with
long cabling when data and clock are not in phase.  Current
transmission standards give no advices except to transmit data and
clock with the same cabling in the same direction.  This is not
always possible nor offered by some standards; i.e., X.21 (single
clock).  Sometimes the data transmission doesn't work at all or works
erroneously depending on the cabling used, the jitter of the clock,
or some reinitialization in one of the products interconnected.

The proposed solution allows:
  o  Automatic positioning of the data with the clock sampling
  o  Better quality of transmission
  o  Dynamic adaptation

      This is done by performing the analysis of the position of data
versus the two edge of the clock and based on that the system
performs the correction of the position of the data thanks to a
controlled delay.

The Phase detection can be performed by the mechanism shown in Fig.
1.

      A counter starts at each occurence of the rising edge of the
clock, and the value is stored on any change of DATA OUT.

      A counter starts at each occurence of the falling edge of the
clock, and the value is stored on any change of DATA OUT.

      Two registers containing the delay between data transition...