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Browse Prior Art Database

Binarly Weighted Element Pulse Delay Line

IP.com Disclosure Number: IPCOM000117826D
Original Publication Date: 1996-Jun-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 67K

Publishing Venue

IBM

Related People

Casal, H: AUTHOR [+4]

Abstract

The performance of the microprocessor depends on being able to minimize the system clock skew among the various FRUs. This is a primary objective of any clock system. Also the calibration and setup of the forward path and the return path delays should be established in a minimum amount of time. The forward and return paths need to be delay matched since any delay mismatch is directly contribute to the skew.

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This is the abbreviated version, containing approximately 61% of the total text.

Binarly Weighted Element Pulse Delay Line

      The performance of the microprocessor depends on being able to
minimize the system clock skew among the various FRUs.  This is a
primary objective of any clock system.  Also the calibration and
setup of the forward path and the return path delays should be
established in a minimum amount of time.  The forward and return
paths need to be delay matched since any delay mismatch is directly
contribute to the skew.

      This disclosure was driven by the need for a delay element
for the micro-processor clock system, however, this can be easily
applicable to any digital systems where a programmable digital delay
is required.

      Fig. 1 shows the high level view of the Digital Phase Aligner.
The solution selected for implementing "DELAY FWD" and "DELAY RTN" in
the micro-processor system is shown in Fig. 2.  It shows a 11 bit
programmable binary weighted delay elements which receives control
signals from the skew control block shown in Fig. 1.

      The delay element is comprised of multiple multiplexors
(selectors,) which connect fixed delay elements as shown where fixed
delay elements are related one to another in a binary fashion.  This
can be seen where the first delay has a value of 46,080 picoseconds
and the next has a value of 23,040 ps which is one-half of the first
delay element.  This arrangement is continued until the delay element
value is reduced essentially to zero.

      The input signal...