Browse Prior Art Database

Method and System for Protection of Micro Controller Buss Writes in a No-ID Disk Drive

IP.com Disclosure Number: IPCOM000117827D
Original Publication Date: 1996-Jun-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Dobbek, JJ: AUTHOR

Abstract

Traditional and No-ID (TM)* disk drive architectures require values to be passed between the microprocessor and other components of the disk drive electronics over a buss. In today's microprocessor external buss designs, it is very expensive to add parity to the data and/or address lines. If IDs are not available on the data track to close loop check the data being accessed, as is the case in No-ID or "headerless" disk drives, it is very important that the values being passed to the other components be correct.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 63% of the total text.

Method and System for Protection of Micro Controller Buss Writes
in a No-ID Disk Drive

      Traditional and No-ID (TM)* disk drive architectures require
values to be passed between the microprocessor and other components
of the disk drive electronics over a buss.  In today's microprocessor
external buss designs, it is very expensive to add parity to the data
and/or address lines.  If IDs are not available on the data track to
close loop check the data being accessed, as is the case in No-ID or
"headerless" disk drives, it is very important that the values being
passed to the other components be correct.

      The present invention solves the described problem cost
effectively by adding serial redundancy to the interface, rather than
by adding traditional parallel redundancy for the data and address
lines.  All checking is performed in hardware, which reduces the
performance impact.  Serial redundancy adds much more protection
because it is also able to detect multiple bit failures.

      Three requirements for implementing the present invention are a
register accessible to the microprocessor, an internal register, and
address redundancy checking to the hardware.  The
microprocessor-accessible register is used to trigger an integrity
check on the previous buss write operation.  There is also a small
amount of open loop code (no checking) to the micro processor.  The
sequence of events of any transfer according to the present invention
is as follows:
 ...