Browse Prior Art Database

Method to Share the Math Coprocessor Error Interrupt in a Personal Computer

IP.com Disclosure Number: IPCOM000117841D
Original Publication Date: 1996-Jun-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 74K

Publishing Venue

IBM

Related People

Appel, W: AUTHOR [+7]

Abstract

Disclosed is a method to share the math coprocesser error (IRQ13) interrupt in a personal computer.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Method to Share the Math Coprocessor Error Interrupt in a Personal
Computer

      Disclosed is a method to share the math coprocesser error
(IRQ13) interrupt in a personal computer.

      Modern Personal Computers (PC) have a fixed number of interrupt
(IRQ) levels which limits the number of devices that can be attached
via expansion cards.  The PC-AT architecture defined over a decade
ago used two Intel 8259 interrupt controllers in cascade mode to
allow up to 15 interrupt levels in a system.  The PS/2* architecture
defined a hare some of the interrupt levels, but IRQ13 has always
been a dedicated level for the math coprocessor error function.

      The trend in modern computer systems is to add function to the
motherboard.  The effect of this added function is to consume the on
board resources - leaving little or none of the IRQ levels for
expansion cards.

      There is a way to use IRQ13 as a level sensitive input to be
shared among several functions on the motherboard.  This design
allows IRQ13 to be shared among many native functions, freeing up
additional levels and avoiding conflicts.  This is accomplished by
providing a hardware register which is programmed by the interrupt
service routine in the second level interrupt handler.  We have added
logic to an on board asic which allows IRQ13 to act as a level
sensitive interrupt.  In our design, there are up to three devices
attached to IRQ13.  Each of these devices has an IRQ output which is
asserted to a logic '1' when it requests service from the interrupt
controller.  Each of these IRQ lines is connected to the equivalent
function of a clock input of a 'D' flip-flop inside the asic.  When a
device asserts it's IRQ, the rising edge sets the flip flop and the
corresponding bit inside the IRQ13 status register.  The asic then
generates an interrupt to the 8259 interrupt controller.  The second
level interrupt handler then...