Browse Prior Art Database

Mechanism for Reducing Cost Associated with Microprocessors Having Rename Buses

IP.com Disclosure Number: IPCOM000117845D
Original Publication Date: 1996-Jun-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Eisen, LE: AUTHOR [+3]

Abstract

Some microprocessors use the concept of the "rename bus" in the place of rename registers. These buses have keeper latches attached to them so that they maintain any logic level that has been momentarily driven onto them by "rename drivers". Such drivers reside in any execution unit required to place result data unto the rename buses. Such drivers tend to be very large and area-costly because they must drive data to many units (usually having more than one load) around the chip. Additionally, there is one driver for each bit of each rename bus.

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This is the abbreviated version, containing approximately 86% of the total text.

Mechanism for Reducing Cost Associated with Microprocessors Having
Rename Buses

      Some microprocessors use the concept of the "rename bus" in the
place of rename registers.  These buses have keeper latches attached
to them so that they maintain any logic level that has been
momentarily driven onto them by "rename drivers".  Such drivers
reside in any execution unit required to place result data unto the
rename buses.  Such drivers tend to be very large and area-costly
because they must drive data to many units (usually having more than
one load) around the chip.  Additionally, there is one driver for
each bit of each rename bus.

      The Dispatch Unit (DU) assigns a rename bus, n, to an
instruction when it is dispatched.  The unit executing said
instruction places the resultant data on rename bus n when it has
finished executing it.  At completion time, rename bus n is
"released" for further use by subsequent instructions.

      The present invention reduces the number of rename drivers used
on a chip.  In a microprocessor design, there may be execution units
(sys unit, complex integer unit, and simple integer unit) that use a
common set of rename drivers.  This is possible because there is only
one instruction that can be assigned rename bus n; no other
instruction can use rename bus n until it has been released by the
Completion Unit (CU).  Therefore, the result data from the sys unit
and the simple integer unit is sent, via standard logic book...