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Circuit for Jitter Detection for Clock Signals

IP.com Disclosure Number: IPCOM000117859D
Original Publication Date: 1996-Jun-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 4 page(s) / 101K

Publishing Venue

IBM

Related People

Casal, H: AUTHOR [+2]

Abstract

JITTER is a term that describes the change in the transition of an electrical signal from a pre-defined reference. In the case of jitter on microprocessor clock signals this is of special interest since the jitter subtracts directly from the useable cycle time of the chip.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Circuit for Jitter Detection for Clock Signals

      JITTER is a term that describes the change in the transition
of an electrical signal from a pre-defined reference.  In the case of
jitter on microprocessor clock signals this is of special interest
since the jitter subtracts directly from the useable cycle time of
the chip.

      Jitter is very difficult to analytically predict for the large
complex chips in design today.  The ability to measure the jitter in
the final hardware is a very difficult problem but is necessary so
the chip design can be characterized and corrected.  It is also
necessary to know the actual amount of jitter so as to set the
appropriate clock cycle time for the system.

      This disclosure describes a way of tracking on chip clock
having the proper frequency and alignment for a period of time.  The
mechanism loads and manipulates the counter with standard digital
controls and can be programmed to provide checking for any valid
frequency.

      In Fig. 1, The REFCLK is inputted to the PLL which creates the
proper internal clock which frequency is a multiple of the REFCLK
(2x, 3x, 4x...) by CONFIG input.  The SNSCLK is the resulting
internal clock.  The "TEST CKT" receives both the SNSCLK and the
REFCLK and it provides a scannable output that represents the test
result.  It is a count which must be compared with expected results
to complete the test.

      The circuitry shown in Fig. 2 allows for the comparison of a
REFCLK signal which presumably is free of jitter and a SNSCLK signal
which the jitter is to be examined.  The circuitry produces an
internal signal labeled "CLK TO S-REGS" which is a "1" whenever there
is a miscompare between the two input signals:  SNSCLK and REFCLK.
This "1" is fed into an AND gate and produces a clock to the shift
register when the CYCLE_EN signal is active ("1").  The shift
register...