Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Clock Deglitcher Using Transition Window Allocation

IP.com Disclosure Number: IPCOM000117867D
Original Publication Date: 1996-Jun-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 4 page(s) / 57K

Publishing Venue

IBM

Related People

Benayoun, A: AUTHOR [+4]

Abstract

The problem addressed is the improvement of the clock stability to avoid erroneous sampling due to external EMC, ESD, crosstalk or bad contacts. On data, this can be done using an oversampling method and is generally used to overcome this problem, but this cannot be directly applied to clock.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 91% of the total text.

Clock Deglitcher Using Transition Window Allocation

      The problem addressed is the improvement of the clock stability
to avoid erroneous sampling due to external EMC, ESD, crosstalk or
bad contacts.  On data, this can be done using an oversampling method
and is generally used to overcome this problem, but this cannot be
directly applied to clock.

The proposed solution offers the following advantages:
  o  Very high reliability:  multiple spikes can be suppressed
  o  glitch or error with any length can be corrected
  o  Up to high speed clocks support
  o  Statistics on clock quality provided
  o  Auto-free running mode in case of clock change
  o  Acquisition phase and jitter adaption
  o  Asymetrical clock handling

The solution is based on the above mechanism:
  o  Window establishment for clock transition allowance
  o  Detection and treament of out of range transitions

      The hardware mechanism takes the control of the falling edge
of the clock controlled by CY1 and CY2 as shown in Fig. 1.

      Similarly, a second block will handle the rising edge of the
clock:  In order to do that, in the second part of the drawing CLK
should be replaced by  -CLK, CY1 by CZ1 and CY2 by CZ2.

The timing corresponding to the above implementation is shown in Fig.
2.

      Based on the mechanism shown in Fig. 2, the output cleaned
clock called CLOCKOUT will correspond to the following function:
  CLOCKOUT = (-CY1+CLK*-CY2)*(CZ1+CLK*CZ2)*CORR...